1. Field of the Invention
Exemplary embodiments of the present invention relate to a liquid crystal display (LCD) apparatus and a method of driving the LCD apparatus. More particularly, exemplary embodiments of the present invention relate to an LCD apparatus in which a chip size is reduced and display quality is enhanced and to a method of driving the LCD apparatus.
2. Discussion of the Background
A liquid crystal display (LCD) apparatus controls light transmission by liquid crystals in accordance with a video signal to display an image corresponding to the video signal. The LCD apparatus includes an LCD panel in which liquid crystal cells are arranged in a matrix shape and a plurality of driving circuits for driving the LCD panel. A plurality of data lines and a plurality of gate lines cross each other on the LCD panel. A thin-film transistor (TFT) for driving a pixel of the LCD is formed at a crossing area of the data line and the gate line. A driving circuit of the LCD apparatus includes a data driving circuit for providing the data lines with data signals and a gate driving circuit for providing the gate lines panel with a scan pulse. In addition, a de-multiplexer circuit is disposed between the data driving circuit and the data lines. The de-multiplexer circuit divides one output signal of the data driving circuit to provide plural data lines with the divided output signal. Since the number of output channels of the data driving circuit is reduced by the de-multiplexer circuit, the data driving circuit may be simplified and the number of data input terminals of the LCD panel may be decreased.
FIG. 1 is a plan view showing an active matrix type LCD apparatus.
Referring to FIG. 1, an LCD apparatus includes an LCD panel 13, a data driving circuit 11, a de-multiplexer circuit 14, and a gate driving circuit 12. The LCD panel 13 includes m data lines DL1 to DLm, n gate lines GL1 to GLn, and a plurality of pixel driving TFTs 16 that are formed at a crossing area of the data lines DL1 to DLm and the gate lines GL1 to GLn, where m and n are natural numbers. The de-multiplexer circuit 14 is disposed between the data driving circuit 11, the gate lines GL1 to GLn, and the data lines DL1 to DLm of the LCD panel 13. The gate driving circuit 12 sequentially provides the gate lines GL1 to GLn with a plurality of scan pulses.
The pixel driving TFT 16 provides a pixel electrode 15 of a liquid crystal cell with data signals provided from the data lines D1 to DLm in response to a scanning signal provided from the gate lines GL1 to GLn. In order to realize the above, gate electrodes (not shown) of the pixel driving TFTs 16 are connected to corresponding gate lines GL1 to GLn. Similarly, source electrodes (not shown) of the pixel driving TFTs 16 are connected to corresponding data lines DL1 to DLm, and drain electrodes (not shown) of the pixel driving TFTs 16 are connected to pixel electrodes 15 of the liquid crystal cell.
The data driving circuit 11 converts digital video data into an analog gamma compensation voltage and temporally divides data signals corresponding to one frame of video data to provide m/2 source lines SL1 to SLm/2 with the divided data signal.
The de-multiplexer circuit 14 is disposed between the data driving circuit 11, the gate lines GL1 to GLn, and the data lines DL1 to DLm. The number of the de-multiplexer circuits 14 may be m/2 to be disposed in parallel with each other. Each of the de-multiplexer circuits 14 includes a first de-multiplexer TFT (hereinafter, “MUX TFT”) MT1 and a second MUX TFT MT2 to divide a data voltage provided from one source line and to supply the divided data voltage to two data lines DL1 and DL2, respectively. The first MUX TFT MT1 and the second MUX TFT MT2 temporally divide the data voltage inputted through one source line SL1 and supply the divided data voltage to two data lines DL1 and DL2, in response to a first control signal φ1 and a second control signal φ2, which are different from each other. The first MUX TFT MT1 and the second MUX TFT MT2 are supplied with the first control signal φ1 and the second control signal φ2 through a first control signal bus line TG1 and a second control signal bus line TG2, respectively.
The gate driving circuit 12 sequentially provides the gate lines GL1 to GLn with scan pulses by using a shift register and a level shifter.
FIG. 2 shows waveform diagrams of control signals and scan pulses that are provided to a de-multiplexer circuit and pixel driving TFT of FIG. 1. For example, FIG. 2 shows first and second control signals φ1 and φ2 from the data driving circuit 11 as well as scan pulses SP1 to SPn from the gate driving circuit 12 that are provided to the de-multiplexer circuit 14.
Referring to FIG. 2, a plurality of scan pulses SP1, SP2, SP3, . . . , SPn has a level of a gate high voltage Vgh generated during one horizontal interval 1H and a level of a gate low voltage Vgl generated during the remaining period that is outside of the one horizontal interval 1H. Since one frame interval corresponds to a time including multiple, for example, hundreds, of horizontal intervals, a duty ratio of a scan pulse, e.g., SP1, may be one out of a total of several hundreds of horizontal intervals.
The first control signal φ1 and the second control signal φ2 of the de-multiplexer circuit 14 are generated at the gate high voltage Vgh during about (i.e., exactly, slightly less than, or slightly greater than) half of a horizontal interval for every horizontal interval. The first control signal φ1 and the second control signal φ2 are generated every horizontal interval 1H so that the duty ratios of the control first signal φ1 and the second control signal φ2 may be about one-half.
The first and second MUX TFTs MT1 and MT2 of the de-multiplexer circuit 14 and the pixel driving TFT may be simultaneously and directly formed on a glass substrate of the LCD panel 13. Swing widths, i.e., the voltage difference between ON and OFF states, of the first and second MUX TFTs MT1 and MT2 and the pixel driving TFT 16 may be equal to each other. For example, the swing widths of the first and second MUX TFTs MT1 and MT2 and the pixel driving TFT 16 may be between a gate high voltage Vgh and a gate low voltage Vgl.
However, when the same polarity of gate voltages is applied to the first and second MUX TFTs MT1 and MT2 for a long time, a positive gate-bias stress or a negative gate-bias stress may be generated in the first and second MUX TFTs MT1 and MT2. Thus, a variation of operating characteristics or deterioration may be generated in comparison with the pixel driving TFT 16 because the gate electrodes of the first and second MUX TFTs MT1 and MT2 require a long gate voltage applying time (i.e., a total applying time) in comparison with the pixel driving TFT 16 of FIG. 1. In order to address this issue, the first and second MUX TFTs MT1 and MT2 may be formed in a larger size. Forming the first and second MUX TFTs MT1 and MT2 of the de-multiplexer circuit 14 of an amorphous silicon (a-Si), the first and second MUX TFTs MT1 and MT2 may be a larger size due to the semiconductor layer characteristics of amorphous silicon (a-Si). A data voltage charged in the pixel electrode 15 may be affected by an increased parasitic capacitance generated at the MUX TFTs MT1 and MT2 that are formed in a larger size, which might produce a distortion of a data signal. Due to the distortion of the data signal, a green pixel and a red pixel may appear with higher luminance than a blue pixel.